The present invention relates generally to electronic logic gates comprised of transistors. More particularly, it relates to a software method of identifying FETs associated with logic gates.
In the field of semiconductor chip design, it is desirable to identify the topology of a system. In the design process, proposed integrated circuit (IC) chip designs may be created using a computer system, such as an electronic design (E-CAD) computer aided drafting (CAD) application. A design may be stored in the computer system so that it may be tested before implementation. In particular, it is desirable to identify the topology of a design stored on a computer system by identifying constituent field effect transistors (FETs) that comprise logic gates. A design may have thousands or millions or more FETs on the chip, so it is impractical to identify topologies without using an automated method. Existing methods of identifying topologies are cumbersome because they fail to accurately identify the constituent FETs. Existing methods simply check for the presence of NAND or NOR topology without regard to the signals driving each constituent FET within each NAND or NOR gate.
Also, existing methods fail to properly account for xe2x80x9cextra FETs.xe2x80x9d Often, extra FETsxe2x80x94those FETs that are not part of a NAND or NOR gatexe2x80x94may be connected to a node of the NAND or NOR gate. This presents a problem in existing methods, which assume no NAND or NOR gates are driving the node with the extra FET. In fact, this assumption is inaccurate. What is needed is an improved method of identifying the constituent FETs of NAND and NOR gates.
A method is disclosed for identifying FETs that comprise NAND and NOR logic gates in a circuit design having numerous FETs. A potential logic gate output node is queried to determine the configuration of FETs around the output node. FETs connected directly between the output node and either a high or low potential (VDD or GND) are identified. If the directly-connected FETs are p-type FETs (PFETs) connected between the output and VDD, then they potentially form part of a NAND gate, and are stored to memory, along with a gate signal that corresponds to each such directly-connected PFET. If the directly-connected FETs are n-type FETs (NFETs) connected between the output and GND, then they potentially form part of a NOR gate, and are stored to memory also along with their gate signals. Branch FETs that are of a different type than the directly-connected FETs and that are channel-connected between the output node and either VDD or GND are also identified. If a gate signal for each FET in a branch corresponds to a gate signal of a directly-connected FET at the same output node, then a logic gate exists. A list of these branch FETs and their corresponding gate signals is stored to memory. The stored branch FET information is compared to the information for the directly-connected FETs to identify the FETs that form the logic gate, based on their gate signals.
In use, to identify NAND gates, the method identifies PFETs that are directly connected between the output node and VDD. The method also identifies branch NFETs that are channel-connected from the output node to GND. The names of the PFET devices and their gate signals are recorded in a PFET hash table. The branch NFET device names and gate signal names are recorded in an NFET hash table if each of the gate signals on the branch NFETs is also present in the PFET hash table. The method compares the gate signals that appear in each hash table and cross-references the FET device names having those same gate signals. These devices and signals are output as the constituent FETs of the NAND gate having inputs of the gate signals.
The method is reversed for detection of NOR gates. The directly-connected FETs are NFETs connected between the output node and GND. The branch FETs will be channel-connected PFETs and the branch will extend from the output node to VDD. These devices and their gate signals are stored in respective hash tables. The method compares the signals that appear in each table and outputs these signals and the FET device names as the constituent FETs of the NOR gate having inputs of the gate signals.